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Tuesday, May 15, Morning, Scandic Edderkoppen Hotel

08:45 - 10:00 Invited Address

The Ternary Calculating Machine of Thomas Fowler
M. Glusker

10:00 - 10:05 Coffee Break

10:05 - 11:05 Session 6A and 6B

Session 6A Theory 6 (Chair: H. Machida)

On the Axiomatization of Generalized Entropic Metrics
Dan A. Simovici

Characterization of Partial She®er Functions in 3-valued Logic
Lucien Haddad, Dietlinde Lau

Power Indexes in Voting Systems and Multiple-Valued Logic
Yoshinori Yamamoto

Session 6B Circuit Design 3 (Chair: N. Homma)

A Ternary Analog-to-Digital Converter System
Tomoki Tanoue, Munehiko Nagatani, Takao Waho

Dual-Data Rate Cyclic D/A Converter using Semi Floating-Gate Devices
René Jensen and Yngvar Berg

Fault tolerant CMOS logic using ternary gates.
Yngvar Berg, Rene Jensen, Johannes Goplen Lomsdalen, Henning Gundersen, Snorre Aunet

11:05 - 11:10 Coffee Break

11:10 - 12:10 Session 7A and 7B

Session 7A Theory 7 (Chair: R .S. Stankovic)

Universal VLSI Based on a Redundant Multiple-Valued Sequential Logic Operation
Tasuku Ito, Michitaka KameyamaTasuku Ito and Michitaka Kameyama

An Application of 16-Valued Logic to Design of Reconfigurable Logic Arrays
Tsutomu Sasao

Milena Stankovic, Suzana Stojkovic, Claudio Moraga

Session 7B Circuit Design 4 (Chair: S. Aunet)

Modeling a Fully Scalable Reed-Solomon Encoder/Decoder over GF(pm) in SystemC
Rolf Drechsler, André Sülflow

Design of a Processing Element Based on Quaternary Differential Logic for a Multi-Core SIMD Processor
Hirokatsu Shirahama, Akira Mochizuki, Takahiro Hanyu, Masami Nakajima, Kazutami Arimoto

Asynchronous Peer-to-Peer Simplex/Duplex-Compatible Communication System Using a One-Phase Signaling Scheme
Tomohiro Takahashi, Kazuyasu Mizusawa, Takahiro Hanyu

12:10 13:30 Lunch at Scandic Edderkoppen Hotel

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